Update Kokkos library in LAMMPS to v3.5.0
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@ -118,11 +118,51 @@ struct test_scatter_view_impl_cls<DeviceType, Layout, Duplication, Contribution,
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scatter_access(k, 3)++;
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scatter_access(k, 4)--;
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scatter_access(k, 5) -= 5;
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// Workaround Intel 17 compiler bug which sometimes add random
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// instruction alignment which makes the lock instruction
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// illegal. Seems to be mostly just for unsigned int atomics.
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// Looking at the assembly the compiler
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// appears to insert cache line alignment for the instruction.
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// Isn't restricted to specific archs. Seen it on SNB and SKX, but for
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// different code. Another occurrence was with Desul atomics in
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// a different unit test. This one here happens without desul atomics.
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// Inserting an assembly nop instruction changes the alignment and
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// works round this.
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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scatter_access_atomic(k, 6) += 2;
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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scatter_access_atomic(k, 7)++;
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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scatter_access_atomic(k, 8)--;
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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--scatter_access_atomic(k, 9);
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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++scatter_access_atomic(k, 10);
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#ifdef KOKKOS_COMPILER_INTEL
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#if (KOKKOS_COMPILER_INTEL < 1800)
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asm volatile("nop\n");
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#endif
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#endif
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scatter_access(k, 11) -= 3;
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}
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}
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