add support for JIT compilation
This commit is contained in:
Axel Kohlmeyer
278
lib/lepton/asmjit/arm/a64instapi.cpp
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278
lib/lepton/asmjit/arm/a64instapi.cpp
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// This file is part of AsmJit project <https://asmjit.com>
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//
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// See asmjit.h or LICENSE.md for license and copyright information
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// SPDX-License-Identifier: Zlib
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#include "../core/api-build_p.h"
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#if !defined(ASMJIT_NO_AARCH64)
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#include "../core/cpuinfo.h"
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#include "../core/misc_p.h"
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#include "../core/support.h"
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#include "../arm/a64instapi_p.h"
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#include "../arm/a64instdb_p.h"
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#include "../arm/a64operand.h"
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ASMJIT_BEGIN_SUB_NAMESPACE(a64)
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// a64::InstInternal - Text
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// ========================
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#ifndef ASMJIT_NO_TEXT
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Error InstInternal::instIdToString(Arch arch, InstId instId, String& output) noexcept {
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uint32_t realId = instId & uint32_t(InstIdParts::kRealId);
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DebugUtils::unused(arch);
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if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
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return DebugUtils::errored(kErrorInvalidInstruction);
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const InstDB::InstInfo& info = InstDB::infoById(realId);
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return output.append(InstDB::_nameData + info._nameDataIndex);
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}
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InstId InstInternal::stringToInstId(Arch arch, const char* s, size_t len) noexcept {
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DebugUtils::unused(arch);
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if (ASMJIT_UNLIKELY(!s))
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return Inst::kIdNone;
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if (len == SIZE_MAX)
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len = strlen(s);
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if (ASMJIT_UNLIKELY(len == 0 || len > InstDB::kMaxNameSize))
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return Inst::kIdNone;
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uint32_t prefix = uint32_t(s[0]) - 'a';
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if (ASMJIT_UNLIKELY(prefix > 'z' - 'a'))
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return Inst::kIdNone;
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uint32_t index = InstDB::instNameIndex[prefix].start;
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if (ASMJIT_UNLIKELY(!index))
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return Inst::kIdNone;
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const char* nameData = InstDB::_nameData;
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const InstDB::InstInfo* table = InstDB::_instInfoTable;
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const InstDB::InstInfo* base = table + index;
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const InstDB::InstInfo* end = table + InstDB::instNameIndex[prefix].end;
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for (size_t lim = (size_t)(end - base); lim != 0; lim >>= 1) {
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const InstDB::InstInfo* cur = base + (lim >> 1);
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int result = Support::cmpInstName(nameData + cur[0]._nameDataIndex, s, len);
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if (result < 0) {
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base = cur + 1;
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lim--;
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continue;
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}
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if (result > 0)
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continue;
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return uint32_t((size_t)(cur - table));
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}
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return Inst::kIdNone;
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}
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#endif // !ASMJIT_NO_TEXT
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// a64::InstInternal - Validate
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// ============================
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#ifndef ASMJIT_NO_VALIDATION
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ASMJIT_FAVOR_SIZE Error InstInternal::validate(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, ValidationFlags validationFlags) noexcept {
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// TODO:
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DebugUtils::unused(arch, inst, operands, opCount, validationFlags);
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return kErrorOk;
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}
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#endif // !ASMJIT_NO_VALIDATION
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// a64::InstInternal - QueryRWInfo
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// ===============================
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#ifndef ASMJIT_NO_INTROSPECTION
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struct InstRWInfoData {
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uint8_t rwx[Globals::kMaxOpCount];
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};
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static const InstRWInfoData instRWInfoData[] = {
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#define R uint8_t(OpRWFlags::kRead)
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#define W uint8_t(OpRWFlags::kWrite)
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#define X uint8_t(OpRWFlags::kRW)
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{{ R, R, R, R, R, R }}, // kRWI_R
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{{ R, W, R, R, R, R }}, // kRWI_RW
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{{ R, X, R, R, R, R }}, // kRWI_RX
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{{ R, R, W, R, R, R }}, // kRWI_RRW
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{{ R, W, X, R, R, R }}, // kRWI_RWX
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{{ W, R, R, R, R, R }}, // kRWI_W
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{{ W, R, W, R, R, R }}, // kRWI_WRW
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{{ W, R, X, R, R, R }}, // kRWI_WRX
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{{ W, R, R, W, R, R }}, // kRWI_WRRW
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{{ W, R, R, X, R, R }}, // kRWI_WRRX
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{{ W, W, R, R, R, R }}, // kRWI_WW
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{{ X, R, R, R, R, R }}, // kRWI_X
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{{ X, R, X, R, R, R }}, // kRWI_XRX
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{{ X, X, R, R, X, R }}, // kRWI_XXRRX
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{{ W, R, R, R, R, R }}, // kRWI_LDn
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{{ R, W, R, R, R, R }}, // kRWI_STn
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{{ R, R, R, R, R, R }} // kRWI_TODO
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#undef R
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#undef W
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#undef X
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};
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static const uint8_t elementTypeSize[8] = { 0, 1, 2, 4, 8, 4, 4, 0 };
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Error InstInternal::queryRWInfo(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, InstRWInfo* out) noexcept {
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// Unused in Release configuration as the assert is not compiled in.
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DebugUtils::unused(arch);
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// Only called when `arch` matches X86 family.
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ASMJIT_ASSERT(Environment::isFamilyARM(arch));
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// Get the instruction data.
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uint32_t realId = inst.id() & uint32_t(InstIdParts::kRealId);
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if (ASMJIT_UNLIKELY(!Inst::isDefinedId(realId)))
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return DebugUtils::errored(kErrorInvalidInstruction);
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out->_instFlags = InstRWFlags::kNone;
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out->_opCount = uint8_t(opCount);
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out->_rmFeature = 0;
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out->_extraReg.reset();
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out->_readFlags = CpuRWFlags::kNone; // TODO: [ARM] Read PSTATUS.
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out->_writeFlags = CpuRWFlags::kNone; // TODO: [ARM] Write PSTATUS
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const InstDB::InstInfo& instInfo = InstDB::_instInfoTable[realId];
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const InstRWInfoData& rwInfo = instRWInfoData[instInfo.rwInfoIndex()];
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if (instInfo.hasFlag(InstDB::kInstFlagConsecutive) && opCount > 2) {
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for (uint32_t i = 0; i < opCount; i++) {
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OpRWInfo& op = out->_operands[i];
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const Operand_& srcOp = operands[i];
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if (!srcOp.isRegOrMem()) {
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op.reset();
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continue;
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}
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OpRWFlags rwFlags = i < opCount - 1 ? (OpRWFlags)rwInfo.rwx[0] : (OpRWFlags)rwInfo.rwx[1];
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op._opFlags = rwFlags & ~(OpRWFlags::kZExt);
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op._physId = BaseReg::kIdBad;
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op._rmSize = 0;
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op._resetReserved();
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uint64_t rByteMask = op.isRead() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
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uint64_t wByteMask = op.isWrite() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
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op._readByteMask = rByteMask;
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op._writeByteMask = wByteMask;
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op._extendByteMask = 0;
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op._consecutiveLeadCount = 0;
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if (srcOp.isReg()) {
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if (i == 0)
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op._consecutiveLeadCount = uint8_t(opCount - 1);
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else
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op.addOpFlags(OpRWFlags::kConsecutive);
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}
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else {
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const Mem& memOp = srcOp.as<Mem>();
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if (memOp.hasBase()) {
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op.addOpFlags(OpRWFlags::kMemBaseRead);
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}
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if (memOp.hasIndex()) {
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op.addOpFlags(OpRWFlags::kMemIndexRead);
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op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
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}
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}
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}
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}
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else {
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for (uint32_t i = 0; i < opCount; i++) {
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OpRWInfo& op = out->_operands[i];
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const Operand_& srcOp = operands[i];
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if (!srcOp.isRegOrMem()) {
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op.reset();
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continue;
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}
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OpRWFlags rwFlags = (OpRWFlags)rwInfo.rwx[i];
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op._opFlags = rwFlags & ~(OpRWFlags::kZExt);
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op._physId = BaseReg::kIdBad;
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op._rmSize = 0;
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op._resetReserved();
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uint64_t rByteMask = op.isRead() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
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uint64_t wByteMask = op.isWrite() ? 0xFFFFFFFFFFFFFFFFu : 0x0000000000000000u;
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op._readByteMask = rByteMask;
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op._writeByteMask = wByteMask;
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op._extendByteMask = 0;
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op._consecutiveLeadCount = 0;
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if (srcOp.isReg()) {
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if (srcOp.as<Vec>().hasElementIndex()) {
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// Only part of the vector is accessed if element index [] is used.
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uint32_t elementType = srcOp.as<Vec>().elementType();
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uint32_t elementIndex = srcOp.as<Vec>().elementIndex();
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uint32_t elementSize = elementTypeSize[elementType];
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uint64_t accessMask = uint64_t(Support::lsbMask<uint32_t>(elementSize)) << (elementIndex * elementSize);
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op._readByteMask &= accessMask;
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op._writeByteMask &= accessMask;
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}
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// TODO: [ARM] RW info is not finished.
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}
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else {
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const Mem& memOp = srcOp.as<Mem>();
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if (memOp.hasBase()) {
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op.addOpFlags(OpRWFlags::kMemBaseRead);
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}
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if (memOp.hasIndex()) {
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op.addOpFlags(OpRWFlags::kMemIndexRead);
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op.addOpFlags(memOp.isPreOrPost() ? OpRWFlags::kMemIndexWrite : OpRWFlags::kNone);
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}
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}
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}
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}
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return kErrorOk;
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}
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#endif // !ASMJIT_NO_INTROSPECTION
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// a64::InstInternal - QueryFeatures
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// =================================
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#ifndef ASMJIT_NO_INTROSPECTION
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Error InstInternal::queryFeatures(Arch arch, const BaseInst& inst, const Operand_* operands, size_t opCount, CpuFeatures* out) noexcept {
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// TODO: [ARM] QueryFeatures not implemented yet.
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DebugUtils::unused(arch, inst, operands, opCount, out);
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return kErrorOk;
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}
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#endif // !ASMJIT_NO_INTROSPECTION
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// a64::InstInternal - Unit
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// ========================
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#if defined(ASMJIT_TEST)
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UNIT(arm_inst_api_text) {
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// TODO:
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}
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#endif
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ASMJIT_END_SUB_NAMESPACE
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#endif // !ASMJIT_NO_AARCH64
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