/*
** Copyright 1998-2002, NVIDIA Corporation.
** All Rights Reserved.
**
** THE INFORMATION CONTAINED HEREIN IS PROPRIETARY AND CONFIDENTIAL TO
** NVIDIA, CORPORATION.  USE, REPRODUCTION OR DISCLOSURE TO ANY THIRD PARTY
** IS SUBJECT TO WRITTEN PRE-APPROVAL BY NVIDIA, CORPORATION.
**
**
*/
#ifndef __CLEXT_H
#define __CLEXT_H

#define CL_NV_DEVICE_COMPUTE_CAPABILITY_MAJOR       0x4000
#define CL_NV_DEVICE_COMPUTE_CAPABILITY_MINOR       0x4001
#define CL_NV_DEVICE_REGISTERS_PER_BLOCK            0x4002
#define CL_NV_DEVICE_WARP_SIZE                      0x4003
#define CL_NV_DEVICE_GPU_OVERLAP                    0x4004
#define CL_NV_DEVICE_KERNEL_EXEC_TIMEOUT            0x4005
#define CL_NV_DEVICE_INTEGRATED_MEMORY              0x4006

#endif