git-svn-id: svn://svn.icms.temple.edu/lammps-ro/trunk@15246 f3b2605a-c512-4ea7-a41b-209d697bcdaa
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@ -178,6 +178,11 @@ void DihedralCharmmIntel::eval(const int vflag,
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}
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}
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#if defined(LMP_SIMD_COMPILER_TEST)
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#pragma vector aligned
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#pragma simd reduction(+:sedihedral, sevdwl, secoul, sv0, sv1, sv2, \
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sv3, sv4, sv5, spv0, spv1, spv2, spv3, spv4, spv5)
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#endif
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for (int n = nfrom; n < nto; n++) {
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const int i1 = dihedrallist[n].a;
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const int i2 = dihedrallist[n].b;
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@ -237,6 +242,7 @@ void DihedralCharmmIntel::eval(const int vflag,
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const flt_t s = rg*rabinv*(ax*vb3x + ay*vb3y + az*vb3z);
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// error check
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#ifndef LMP_SIMD_COMPILER_TEST
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if (c > PTOLERANCE || c < MTOLERANCE) {
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int me = comm->me;
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@ -258,6 +264,7 @@ void DihedralCharmmIntel::eval(const int vflag,
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me,x[i4].x,x[i4].y,x[i4].z);
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}
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}
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#endif
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if (c > (flt_t)1.0) c = (flt_t)1.0;
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if (c < (flt_t)-1.0) c = (flt_t)-1.0;
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@ -337,6 +344,9 @@ void DihedralCharmmIntel::eval(const int vflag,
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}
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#if defined(LMP_SIMD_COMPILER_TEST)
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#pragma simdoff
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#endif
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{
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if (NEWTON_BOND || i2 < nlocal) {
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f[i2].x += f2x;
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@ -413,6 +423,9 @@ void DihedralCharmmIntel::eval(const int vflag,
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}
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// apply force to each of 4 atoms
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#if defined(LMP_SIMD_COMPILER_TEST)
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#pragma simdoff
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#endif
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{
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if (NEWTON_BOND || i1 < nlocal) {
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f[i1].x += f1x;
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@ -668,7 +681,7 @@ void DihedralCharmmIntel::eval(const int vflag,
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const SIMD_flt_t tcos_shift = SIMD_gather(nmask, cos_shift, type);
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const SIMD_flt_t tsin_shift = SIMD_gather(nmask, sin_shift, type);
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const SIMD_flt_t tk = SIMD_gather(nmask, k, type);
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const SIMD_int m = SIMD_gather(nmask, multiplicity, type);
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const SIMD_int m = SIMD_gatherz_offset<flt_t>(nmask, multiplicity, type);
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SIMD_flt_t p(one);
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SIMD_flt_t ddf1(szero);
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@ -194,6 +194,37 @@ namespace ip_simd {
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_MM_SCALE_8);
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}
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template <typename T>
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inline SIMD_int SIMD_gatherz_offset(const SIMD_mask &m, const int *p,
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const SIMD_int &i) {
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}
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template <>
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inline SIMD_int SIMD_gatherz_offset<float>(const SIMD_mask &m, const int *p,
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const SIMD_int &i) {
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return _mm512_mask_i32gather_epi32( _mm512_set1_epi32(0), m, i, p,
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_MM_SCALE_4);
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}
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template <>
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inline SIMD_int SIMD_gatherz_offset<double>(const SIMD_mask &m, const int *p,
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const SIMD_int &i) {
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return _mm512_mask_i32gather_epi32( _mm512_set1_epi32(0), m, i, p,
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_MM_SCALE_8);
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}
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inline SIMD_float SIMD_gatherz(const SIMD_mask &m, const float *p,
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const SIMD_int &i) {
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return _mm512_mask_i32gather_ps( _mm512_set1_ps((float)0), m, i, p,
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_MM_SCALE_4);
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}
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inline SIMD_double SIMD_gatherz(const SIMD_mask &m, const double *p,
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const SIMD_int &i) {
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return _mm512_mask_i32logather_pd( _mm512_set1_pd(0.0), m, i, p,
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_MM_SCALE_8);
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}
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// ------- Store Operations
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inline void SIMD_store(int *p, const SIMD_int &one) {
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